| PART |
Description |
Maker |
| MC100LVEL29DWR2 |
3.3V ECL Dual Differential Data and Clock D Flip−Flop With Set and Reset 100LVEL SERIES, DUAL POSITIVE EDGE TRIGGERED D FLIP-FLOP, COMPLEMENTARY OUTPUT, PDSO20
|
ON Semiconductor
|
| 74LV109 74LV109D 74LV109DB 74LV109N 74LV109PW 74LV |
Dual JK flip-flop with set and reset; positive-edge trigger LV/LV-A/LVX/H SERIES, DUAL POSITIVE EDGE TRIGGERED J-KBAR FLIP-FLOP, COMPLEMENTARY OUTPUT, PDSO16
From old datasheet system
|
NXP Semiconductors N.V.
PHILIPS[Philips Semiconductors]
|
| ACTS74HMSR-02 |
Dual D Type Flip Flop with Set and Reset, Advanced Logic, CMOS; Temperature Range: -55°C to 125°C; Package: Die (Military Visual) ACT SERIES, DUAL POSITIVE EDGE TRIGGERED D FLIP-FLOP, COMPLEMENTARY OUTPUT, UUC14
|
Intersil, Corp.
|
| HCF4013 HCF4013M013TR HCF4013B HCF4013BEY HCF4013B |
4000/14000/40000 SERIES, DUAL POSITIVE EDGE TRIGGERED D FLIP-FLOP, COMPLEMENTARY OUTPUT, PDSO14
DUAL 'D' - TYPE FLIP-FLOP
DUAL D-TYPE FLIP FLOP
|
STMICROELECTRONICS[STMicroelectronics]
|
| IN74HCT109 |
DUAL J-K FLIP-FLOP WITH SET AND RESET
|
INTEGRAL[Integral Corp.]
|
| IN74VHCT74N IN74VHCT74 IN74VHCT74D |
Dual D Flip-Flop with Set and Reset
|
INTEGRAL[Integral Corp.]
|
| CD54AC113A CD54ACT112 CD54AC112 CD54ACT113A |
Dual J-K Flip-Flop with Set and Reset
Dual “J-K” Flip-Flop with Set and Reset
Dual “J-K?/a> Flip-Flop with Set and Reset
Dual “J-K Flip-Flop with Set and Reset
|
INTERSIL[Intersil Corporation]
|
| MC74VHC74-D MC74VHC74MEL MC74VHC74DR2 MC74VHC74DTR |
Dual D-Type Flip-Flop with Set and Reset
|
ON Semiconductor
|
| IN74ACT112N IN74ACT112 IN74ACT112D |
DUAL J-K FLIP-FLOP WITH SET AND RESET 双JK触发器与SET和RESET
|
INTEGRAL JOINT STOCK COMPANY
INTEGRAL[Integral Corp.]
|
| CD4027BCN CD4027BCM |
Dual J-K Master/Slave Flip-Flop with Set and Reset
|
Fairchild Semiconductor
|
| MC54_74HC74A MC54HC74AJ ON1495 |
DUAL D FLIP-FLOP WITH SET AND RESET
From old datasheet system
|
ON Semi
MOTOROLA[Motorola Inc]
|
